This invention relates generally to the fabrication of semiconductor devices, and in particular to nonvolatile memories.
The ability to manufacture high quality oxides is of extreme importance in the production of semiconductor devices. As the need for ever thinner oxides has increased, the requirement for major improvements to obtain reliable ultra thin oxide films has become vital. This is especially true in the tunnel oxides of Electrically Erasable Programmable Read-Only Memories (EEPROMs), where the oxide may be less than 100 .ANG. thick. In order to improve these oxides, all phases of their manufacture continue to be examined for possible improvements. In making these improvements, it is also vital to maintain high levels of integrity for the other parts of the memory cell, such as the performance of the high and low voltage gates as measured in terms of gate leakage. These various requirements often place conflicting demands on the manufacturing process.
In the silicon wafer production process, manufacturers use many differing procedures to manufacture EEPROMs: in FLOating gate Thin OXide (FLOTOX) devices, one variation of the standard series of steps includes:
1) Field Oxidation PA0 2) Nitride Strip PA0 3) Sacrificial Gate Oxidation and Strip PA0 4) EEPROM Oxidation PA0 5) Tunnel Diffusion Implant PA0 6) Tunnel Window Definition PA0 7) Tunnel Oxidation PA0 8) Tunnel Oxide Anneal PA0 9) Poly 1 Deposition, Doping, and Definition PA0 10) ONO Deposition and Definition PA0 11) High Voltage Transistor Gate Oxidation PA0 12) Etch High Voltage Transistor Gate Oxide From Low Voltage Transistor Regions PA0 13) Low Voltage Transistor Gate Oxidation PA0 14) Poly 2 Deposition, Doping, and Definition.
In the manufacture of a standard, non-memory transistor, this process would jump directly from steps 3 to steps 13. Steps 4 through 12 are added for the production of nonvolatile memory circuits, with steps 5 through 7 specific to the thin tunnel oxide needed in a FLOTOX device. Not all of these steps are strictly necessary, or need be in this order, but they are often added to improve the quality of the circuit. Step 3, consisting of a sacrificial gate oxidation and strip, is one such step.
The field oxide of Step 1 is formed using a local oxidation of silicon ("LOCOS") process. One undesired effect of the LOCOS process is a thinning at the edges of oxide layers grown after step 2. This damage is called the "white ribbon problem" or "Kooi effect," due to its description in "Formation of Silicon Nitride at a Si--SiO.sub.2 Interface during Local Oxidation of Silicon and during Heat-Treatment of Oxidized Silicon in NH.sub.3 Gas" by E. Kooi, et al.; Journal of the Electrochemical Society; Vol. 123, Number 7; Jul., 1976; and is well known. In growing the field oxides, they encroach under the nitride layer, producing a formation know as a bird's beak due to its shape. It is at the end of the bird's beak that this unwanted thinning occurs. Since this thinning, caused by a nitride growth under the oxide, degrades the quality of the subsequent oxides, it needs to be corrected.
The sacrificial gate oxidation and strip of steps 3 is a widely used method to eliminate the white ribbon problem. After stripping the masking nitride and underlying pad oxide in step 2, a "sacrificial" gate oxide is grown and then etched away before growing the final gate oxide. This results in smaller gate leakage currents and a lower defect density. Many variations are used to optimize this procedure at the LOCOS stage, including repeating this step in a double, back-to-back sacrificial oxide process as in "Gate Oxide Reliability in a Sealed Interface Local Oxidation Scheme," by I. J. Voors, et al.; ESSDERC '89, 19th European Solid State Devices Research; Sept. 1989; and in "A Double Sacrificial Oxide Process for Smoother 150 .ANG. SiO.sub.2 Gate Oxide Interfaces," H. H. Tseng, et al.; Exetended Abstracts of the Meeting of the Electrochemical Society; Spring 1992.
After step 3, a non-volatile memory such as an EEPROM is fabricated in steps 4-12. This allows the possibility of changing the order of some steps, such as moving the sacrificial oxidation and strip to after the tunnel diffusion implant of step 5. This is done, for instance, in U.S. Pat. No. 5,538,913 issued to Gardner et al. on May 27, 1994, where it is combined with the post-oxidation anneal, shown above as step 8.
This post-oxidation anneal of step 8 is another stage not required, but included to improve the tunnel oxide. This anneal enhances the integrity of the thin gate oxides of step 7 and also the dopant diffusion of step 5. These improvements can be quantified in terms of important quantities such as the charge to breakdown, Q.sub.BD, of the tunnel oxides in an EEPROM. There are several variations on the process, such as that described in co-pending U.S. patent application Ser. No. 09/215,797 of Berg, et al. entitled "Method of Fabrication a High Quality Thin Oxide." It is generally found that the Q.sub.BD of tunnel oxide is improved, as both the time and the temperature used for annealing are increased. The ambient environment is also important, with the amount and form of nitrogen present having a large effect on the quality of the result.
Although this post-oxidation annealing in nitrogen improves the quality of the thin oxide, it has a detrimental effect on subsequent gate oxides, such as those formed in steps 11-13 for the high and low voltage gates. This can produce excessive leakage current through the gate oxide measurable, for example, in the large variation of the threshold voltages of the narrow width high voltage devices. The effect is particularly acute in the first oxides formed after the anneal, for the high voltage devices, compromising transistor drive capability as well as reliability. These problems are compounded by the result that, while an increase in both the time and temperature of the anneal improves the quality of the thin oxide, both of these further degrade transistor performance.
Thus, the improvement of thin tunnel oxides used in EEPROM and FLASH technologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate oxide leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. Further improvements are needed to perfect the thin oxide forming process in order to produce a robust oxide without sacrificing transistor performance.